The present invention relates to analog-to-digital converter (ADC) circuits, and in particular, to pipelined ADCs.
Many forms of digital signal processing systems require data conversion devices to quantize analog data signals for use in the digital signal processing. Such data conversion devices often include an ADC. One type of ADC which is perhaps most often used is a pipelined ADC.
One common form of ADC uses a double sampling technique, which increases data throughput by a factor of two. Such sampling relies upon end sampling comparison in which the leading, e.g., rising, edge of the clock is used to derive all critical timing signals, while the trailing, e.g., falling, clock edge is ignored. The data hold time is defined as one clock cycle minus the time needed for the comparator strobe and reset. This poses two limitations on the architecture of the ADC. First, hold time is sacrificed for strobe time, thereby limiting conversion efficiency. Peak efficiency is achieved when the hold time is one full clock cycle minus the reset time. Second, a very fast comparator must be used so as to allow strobe time to be reduced, and thereby achieve high efficiency.